Interfacial layer dependence of HFSixOy gate stacks on VT instability and charge trapping using ultra-short pulse in characterization

被引：37

作者：

Young, CD ^{[1
]}

Choi, R ^{[1
]}

Sim, JH ^{[1
]}

Lee, BH ^{[1
]}

Zeitzoff, P ^{[1
]}

Zhao, B ^{[1
]}

Matthews, K ^{[1
]}

Brown, GA ^{[1
]}

Bersuker, G ^{[1
]}

机构：

[1] SEMATECH, Austin, TX 78741 USA

来源：

2005 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 43RD ANNUAL | 2005年

关键词：

pulse I-V; charge trapping; hafnium; interface layer;

D O I：

10.1109/RELPHY.2005.1493066

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Fast transient charging was investigated using pulse I-V measurements with charging times ranging from 35ns to 5ms on HfSi(x)Oy gate stacks of varying interfacial layer thickness. It is shown that a nanosecond regime measurement capability is required to achieve trap-free pulse I-V characteristics. The ultra-short pulse I-V measurement technique and bias dependence was used to investigate fast transient charging. The fast electron trapping is found to be a source of degradation in the DC characteristics of the high-kappa transistors, which strongly depends on the interfacial layer thickness.

引用

页码：75 / 79

页数：5