The impact of device scaling and power supply change on CMOS gate performance

被引：42

作者：

Chen, K

Wann, HC

Ko, PK

Hu, CM

机构：

[1] Dept. of Elec. Eng. and Comp. Sci., University of California, Berkeley

来源：

IEEE ELECTRON DEVICE LETTERS | 1996年 / 17卷 / 05期

关键词：

D O I：

10.1109/55.491829

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based a new empirical mobility model that's solely dependent on T-gs, V-t, and T-ox and a corresponding saturation drain current (I-dsat) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper, It shows that the T-ox which maximizes inverter's speed may be thicker than reliability consideration requires, In addition, very high speed can be achieved even at low V-dd (for low power applications) if V-t can be lowered.

引用

页码：202 / 204

页数：3