A tool for partitioning and pipelined scheduling of hardware-software systems

被引:7
作者
Chatha, KS [1 ]
Vemuri, R [1 ]
机构
[1] Univ Cincinnati, Digital Design Environm Lab, Dept ECECS, Cincinnati, OH 45221 USA
来源
11TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS - PROCEEDINGS | 1998年
关键词
D O I
10.1109/ISSS.1998.730616
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present a tool for synthesis of pipelined implementations of hardware-software systems. The toed uses iterative hardware-software partitioning and pipelined scheduling to obtain optimal partitions which satisfy the timing and area constraints. The partitioner uses a branch and bound approach with a unique objective function which minimizes the initiation interval of the final design. It takes communication time and hardware sharing into account. This paper also presents techniques for generation of good initial solution and search space bounding far the partitioning algorithm. A candidate partition is evaluated by generating its pipelined schedule. The scheduler uses a list based scheduler and a retiming transformation to optimize the initiation interval, number of pipeline stages and memory requirements of a particular design alternative. The effectiveness of the tool is demonstrated by experimentation.
引用
收藏
页码:145 / 151
页数:7
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