A 130 nm generation logic technology featuring 70nm transistors, dual Vt transistors and 6 layers of Cu interconnects

被引：106

作者：

Tyagi, S ^{[1
]}

Alavi, M ^{[1
]}

Bigwood, R ^{[1
]}

Bramblett, T ^{[1
]}

Brandenburg, J ^{[1
]}

Chen, W ^{[1
]}

Crew, B ^{[1
]}

Hussein, M ^{[1
]}

Jacob, P ^{[1
]}

Kenyon, C ^{[1
]}

Lo, C ^{[1
]}

Mcintyre, B ^{[1
]}

Ma, Z ^{[1
]}

Moon, P ^{[1
]}

Nguyen, P ^{[1
]}

Rumaner, L ^{[1
]}

Schweinfurth, R ^{[1
]}

Sivakumar, S ^{[1
]}

Stettler, M ^{[1
]}

Thompson, S ^{[1
]}

Tufts, B ^{[1
]}

Xu, J ^{[1
]}

Yang, S ^{[1
]}

Bohr, M ^{[1
]}

机构：

[1] Intel Corp, Portland Technol Dev, Hillsboro, OR 97124 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904383

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA/(mu)m and 0.5 mA/(mu)m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA/(mu)m and 0.6 mA/(mu)m respectively. Technology design rules allow a 6-T SRAM cell with an area of 2.45 (mu)m(2), while array specific design rule give the densest SRAM reported to date, the 6-T cell has an area of only 2.09 (mu)m(2). Excellent yield and performance is demonstrated on a 18 Mbit CMOS SRAM.

引用

页码：567 / 570

页数：4

共 5 条

[1]

Bohr MT, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P241, DOI 10.1109/IEDM.1995.499187

[2]

Cangsang Zhao, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), P200, DOI 10.1109/ISSCC.1999.759193

[3]

CROWDER S, 1999, VLSI TECH DIG, P105

[4]

Ghani T., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P415, DOI 10.1109/IEDM.1999.824182

[5] A high performance 180 nm generation logic technology [J].

Yang, S ;

Ahmed, S ;

Arcot, B ;

Arghavani, R ;

Bai, P ;

Chambers, S ;

Charvat, P ;

Cotner, R ;

Gasser, R ;

Ghani, T ;

Hussein, M ;

Jan, C ;

Kardas, C ;

Maiz, J ;

McGregor, F ;

McIntyre, B ;

Nguyen, P ;

Packan, P ;

Post, I ;

Sivakumar, S ;

Steigerwald, J ;

Taylor, M ;

Tufts, B ;

Tyagi, S ;

Bohr, M .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :197-200

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