A high performance 180 nm generation logic technology

被引：84

作者：

Yang, S ^{[1
]}

Ahmed, S ^{[1
]}

Arcot, B ^{[1
]}

Arghavani, R ^{[1
]}

Bai, P ^{[1
]}

Chambers, S ^{[1
]}

Charvat, P ^{[1
]}

Cotner, R ^{[1
]}

Gasser, R ^{[1
]}

Ghani, T ^{[1
]}

Hussein, M ^{[1
]}

Jan, C ^{[1
]}

Kardas, C ^{[1
]}

Maiz, J ^{[1
]}

McGregor, F ^{[1
]}

McIntyre, B ^{[1
]}

Nguyen, P ^{[1
]}

Packan, P ^{[1
]}

Post, I ^{[1
]}

Sivakumar, S ^{[1
]}

Steigerwald, J ^{[1
]}

Taylor, M ^{[1
]}

Tufts, B ^{[1
]}

Tyagi, S ^{[1
]}

Bohr, M ^{[1
]}

机构：

[1] Intel Corp, Portland Technol Dev, Hillsboro, OR 97124 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746320

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 180 nm generation logic technology has been developed with high performance 140 nm L-GATE transistors, six layers of aluminum interconnects and low-epsilon SiOF dielectrics. The transistors are optimized for a reduced 1.3-1.5 V operation to provide high performance and low power. The interconnects feature high aspect ratio metal lines for low resistance and fluorine doped SiO2 inter-level dielectrics for reduced capacitance. 16 Mbit SRAMs with a 5.59 mu m(2) 6-T cell size have been built on this technology as a yield and reliability test vehicle.

引用

页码：197 / 200

页数：4

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