Plasma-etching processes for ULSI semiconductor circuits

An overview is presented of plasma-etching processes used in the fabrication of ULSI (ultralarge-scale integrated) semiconductor circuits, with emphasis on work in our facilities. Such circuits contain structures having minimum pattern widths of 0.25 mu m and less. Challenges in plasma etching in evolving to such dimensions have come from the implementation of antireflective coatings and thinner, more etch-sensitive photoresists; the increased aspect ratios needed to meet design requirements; the additional hard-mask etching steps needed at levels at which lithography is unsuitable for patterning; and increased selectivity requirements, such as the requirement that contact structures be self-aligning. Future circuit density and performance requirements dictate tighter specifications for linewidth variations permitted across a wafer, microloading effects, and device damage. As a result, plasma-etching systems for critical levels are migrating from traditional multifilm, capacitively coupled low-density-plasma systems to medium- and high-density-plasma systems employing exotic or highly polymerizing chemical species specifically designed for one type of film.