Fringing-induced barrier lowering (FIBL) in sub-100nm MOSFETs with high-K gate dielectrics

被引：65

作者：

Yeap, GCF ^{[1
]}

Krishnan, S ^{[1
]}

Lin, MR ^{[1
]}

机构：

[1] Adv Micro Devices Inc, Technol Dev Grp, Sunnyvale, CA 94088 USA

来源：

ELECTRONICS LETTERS | 1998年 / 34卷 / 11期

关键词：

D O I：

10.1049/el:19980800

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Fringing-induced barrier lowering (FIBL), a new anomalous degradation in device turn-off/on characteristics in sub-100nm devices with high-K gate dielectrics, is reported. FIBL is clearly evident fcr K > 25 and worsens as K increases (without buffer oxide). With a buffer oxide, FIBL can lx completely suppressed for K < 25, and partially for higher ii. FIBL worsens as the gate length becomes shorter. Complete removal of high-K dielectrics on the active area induces a smaller FIBL.

引用

页码：1150 / 1152

页数：3