A GALS infrastructure for a massively parallel multiprocessor

被引:89
作者
Plana, Luis A.
Furber, Steve B.
Temple, Steve
Khan, Mukaram
Shi, Yebin
Wu, Jian
Yang, Shufan
机构
[1] University of Manchester, School of Computer Science, Manchester M13 9PL, Oxford Road
来源
IEEE DESIGN & TEST OF COMPUTERS | 2007年 / 24卷 / 05期
基金
英国工程与自然科学研究理事会;
关键词
D O I
10.1109/MDT.2007.149
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The Spinnaker (Spiking Neural Network Architecture) system for large-scale neural modeling is based on a scalable processor chip containing multiple ARM cores. Using a globally asynchronous, locally synchronous (GALS) approach allows custom, off-the-shelf IP to be readily integrated without significant timing-closure design effort. The ARM processors are used to simulate neurons, and generated neural events are carried over an on-chip, packet-switched fabric. This self-timed interconnect is also extended off chip to a provide chip-to-chip interconnect that scales to networks of thousands of chips. © 2007 IEEE.
引用
收藏
页码:454 / 463
页数:10
相关论文
共 9 条
[1]  
*ARM, 1999, ADV MICR BUS ARCH AM
[2]  
*ARM, ARM968ES
[3]   Chain: A delay-insensitive chip area interconnect [J].
Bainbridge, J ;
Furber, S .
IEEE MICRO, 2002, 22 (05) :16-23
[4]   Delay-insensitive, point-to-point interconnect using m-of-n codes [J].
Bainbridge, WJ ;
Toms, WB ;
Edwards, DA ;
Furber, SB .
NINTH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS, 2003, :132-140
[5]   Neural systems engineering [J].
Furber, Steve ;
Temple, Steve .
JOURNAL OF THE ROYAL SOCIETY INTERFACE, 2007, 4 (13) :193-206
[6]  
SHI Y, 2006, P 18 UK AS FOR U NEW, P24
[7]  
*SILISTIX, SIL SELF TIM INT TEC
[8]   DELAY-INSENSITIVE CODES - AN OVERVIEW [J].
VERHOEFF, T .
DISTRIBUTED COMPUTING, 1988, 3 (01) :1-8
[9]  
Wu J., 2006, P 18 UK AS FOR, V2, P16