Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETs

被引：13

作者：

Liu, CT ^{[1
]}

机构：

[1] AT&T Bell Labs, Lucent Technol, Murray Hill, NJ 07974 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746464

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The trend of CMOS technologies toward highspeed, low-power, and systems-on-a-chip has raised several urgent requirements on the gate dielectrics: (1) limited leakage current, (2) multiple thickness (t(ox)), (3) minimized variation or degradation of device threshold voltage (V-th), transconductance (G(m)), and on-current (I-on) at the finish of the device fabrication due to, e.g., oxide-nitridation-induced degradation or plasma-damage-induced degradation, (4) sustained device lifetime that has been difficult to achieve because of the aggressive device scaling, and (5) a practical and physical mean of qualifying thin gate dielectrics. The significance of each of the above requirements will be discussed, and recent efforts addressing these requirements will be reviewed.

引用

页码：747 / 750

页数：4