High-speed architecture for a programmable frequency divider and a dual-modulus prescaler

We present a prescaler architecture that is suitable for high-speed CMOS applications. We apply the architecture to a 4/5 and an 8/9 dual-modulus prescaler and obtain a measured maximum clock frequency of 1.90 GHz in a standard 0.8 mu m CMOS bulk process. This is 13% faster than the traditional prescaler architecture keeping the same power consumption. We also apply the key part of the prescaler to a divide-by-N circuit reaching 1.75 GHz. This is three times faster than any previously reported CMOS implementation and comparable to GaAs implementations.