Source/drain engineering for sub-100 nm CMOS using selective epitaxial growth technique

High performance sub-100 nm MOSFETs have been realized utilizing elevated source/drain (S/D) technologies. By utilizing the selective epitaxial growth (SEG) process, the suppression of short channel effect (SCE), junction leakage current, and parasitic resistance are realized. Moreover, the necessity of special technique for channel engineering in order not to increase the gate-to-source/drain capacitance is described when using elevated source/drain structures. A novel prohibition process of deposition on poly-Si gate electrodes for reducing gate depletion is also mentioned.