Design and realization of sub 100nm gate length HEMTs

被引：21

作者：

Parenty, T ^{[1
]}

Bollaert, S ^{[1
]}

Mateos, J ^{[1
]}

Wallart, X ^{[1
]}

Cappy, A ^{[1
]}

机构：

[1] Inst Elect & Microelect Nord, UMR CNRS 9929, Dept Hyperfrequences & Semicond, F-59652 Villeneuve Dascq, France

来源：

2001 INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS, CONFERENCE PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/ICIPRM.2001.929234

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Standard layer structure InAlAs/InGaAs/InP designed for 100 nanometer gate length High Electron Mobility Transistors (HEMTs) become inadequate, if we reduce the gate length under 100nm. An InAlAs/InGaAs/InP layer structure optimized for 50 nanometer gate length HEMTs has been realized. DC and microwave characteristics are reported on HEMTs realized on a standard layer and an optimized layer, with similar gate length. Comparable cutoff frequencies f(T) are obtained for both devices. The main result is a large improvement of maximum oscillation frequency f(max), which is 260 GHz and 470 GHz for respectively the standard and the optimized devices. This behavior is attributed to the reduction of short channel effects.

引用

页码：626 / 629

页数：4