Porous low k pore sealing process study for 65-nm and below technologies

被引：38

作者：

Mourier, T ^{[1
]}

Jousseaume, V ^{[1
]}

Fusalba, F ^{[1
]}

Lecornec, C ^{[1
]}

Maury, P ^{[1
]}

Passemard, G ^{[1
]}

Haumesser, PH ^{[1
]}

Maîtrejean, S ^{[1
]}

Cordeau, M ^{[1
]}

Pantel, R ^{[1
]}

Pierre, F ^{[1
]}

Fayolle, M ^{[1
]}

Feldis, H ^{[1
]}

机构：

[1] CEA, DRT, LETI, DTS,GRE, F-38054 Grenoble 9, France

来源：

PROCEEDINGS OF THE IEEE 2003 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2003年

关键词：

D O I：

10.1109/IITC.2003.1219766

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

65 nm and below technologies will require a combination of porous ultra low k dielectric and copper metallization. Feature size may need the use of conformal metallic barrier deposition methods like CVD or ALD. One of the key issues for integration of such materials come from the tendency for precursor to diffuse through the porous structure degrading effective k value. Various pore sealing methodologies were already investigated and reported. In this paper, we describe a process based on the deposition of a thin dielectric liner that allows sealing of surface pores without impacting too much dielectric properties of ULK material. Physico-chemical analysis were carried out and confirmed by electrical measurements.

引用

页码：245 / 247

页数：3

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