Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections

被引：18

作者：

Deutsch, A ^{[1
]}

Harrer, H ^{[1
]}

Surovic, CW ^{[1
]}

Hellner, G ^{[1
]}

Edelstein, DC ^{[1
]}

Goldblatt, RD ^{[1
]}

Biery, GA ^{[1
]}

Greco, NA ^{[1
]}

Foster, DM ^{[1
]}

Crabbe, E ^{[1
]}

Su, LT ^{[1
]}

Coteus, PW ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Heights, NY 10598 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746358

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Experimental high-speed characterization and electrical modeling and simulation are presented for a six-layer Cu/SiO2 on-chip wiring structure with 12.4-mm-long limes. Testing is performed over the temperature range -160 degrees C to +100 degrees C and across a 200-mm-diameter wafer. Very good agreement is reported between measured and simulated signal propagation and crosstalk waveforms. Modeling is done using a three-dimensional field solver and the RV), L(f), and C matrices are used in a synthesized distributed network to simulate the signal behavior. Such a broadband analysis comprises the first comprehensive functional testing of a multi-layer Cu/SiO2 wiring structure. The Cu interconnections are shown to be able to sustain 5.39 (GHz microprocessor frequencies at T = +25 degrees C operation at a scaled wiring density increase of 17.5%, while comparable AI(Cu) wiring can achieve only 4.44 GHz (21.4% improvement).

引用

页码：295 / 298

页数：4

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