RF-CMOS performance trends

被引：231

作者：

Woerlee, PH ^{[1
]}

Knitel, MJ ^{[1
]}

van Langevelde, R ^{[1
]}

Klaassen, DBM ^{[1
]}

Tiemeijer, LF ^{[1
]}

Scholten, AJ ^{[1
]}

Duijnhoven, ATAZV ^{[1
]}

机构：

[1] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2001年 / 48卷 / 08期

关键词：

CMOS integrated circuits; MOS devices; modeling; radio frequency;

D O I：

10.1109/16.936707

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented, Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

引用

页码：1776 / 1782

页数：7

共 15 条

[1]

Burghartz J. N., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P853, DOI 10.1109/IEDM.1999.824283

[2]

HOLLOWAY TC, 1997, VLSI S, P13

[3] A UNIFIED MODEL FOR THE FLICKER NOISE IN METAL OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS [J].