Novel low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra low power dual gate CMOS technology

被引：5

作者：

Kotaki, H ^{[1
]}

Kakimoto, S ^{[1
]}

Nakano, M ^{[1
]}

Adachi, K ^{[1
]}

Shibata, A ^{[1
]}

Sugimoto, K ^{[1
]}

Ohta, K ^{[1
]}

Hashizume, N ^{[1
]}

机构：

[1] Sharp Corp, Cent Res Labs, Tenri, Nara 6328567, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746387

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed a novel high speed dynamic threshold voltage MOSFET named LCSED for ultra low power operation. This was realized using sidewall elevated drain. The LCSED achieved the following excellent characteristics as compared to the Bulk-DTMOS which we proposed before: 60% reduced occupation area; 65% reduced junction capacitance; 67% reduced forward leakage current between shallow-well and source/drain; lower transistor series resistance; smaller short channel effect; higher drive current. These effects realize ultra low power high speed operation.

引用

页码：415 / 418

页数：4

共 6 条

[1]

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[2]

AZUMA A, 1994, S VLSI TECHN, P129

[3]

KAKIMOTO S, 1993, 54 AUT M 1993 JAP SO, P727

[4] Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS [J].

Kotaki, H ;

Kakimoto, S ;

Nakano, M ;

Matsuoka, T ;

Adachi, K ;

Sugimoto, K ;

Fukushima, T ;

Sato, Y .

IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, :459-462

[5]

Kotaki H., 1993, International Electron Devices Meeting 1993. Technical Digest (Cat. No.93CH3361-3), P839, DOI 10.1109/IEDM.1993.347269

[6]

SU LT, 1994, INTERNATIONAL ELECTRON DEVICES MEETING 1994 - IEDM TECHNICAL DIGEST, P649, DOI 10.1109/IEDM.1994.383326

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