Wafer level chip scale packaging (WL-CSP): An overview

被引：123

作者：

Garrou, P ^{[1
]}

机构：

[1] Dow Chem Co USA, Res Triangle Pk, NC 27709 USA

来源：

IEEE TRANSACTIONS ON ADVANCED PACKAGING | 2000年 / 23卷 / 02期

关键词：

CSP; wafer level CSP;

D O I：

10.1109/6040.846634

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing, Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when underfill is not used than for equivalent flip chip parts, Rambus(TM) RDRAM and integrated passives are two applications that should see nide acceptance of WLCSP packages.

引用

页码：198 / 205

页数：8

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IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2000, 23 (02) :227-232

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