Directed self-assembly process for nano-electronic devices and interconnect

Requirements for nano-electronic devices and interconnect in conventional logic circuit architecture are examined to reveal the possible device structure containing self-assembly (SA) features. For integration with lithography, we discuss the features of the SA process and then present a full process flow for a novel type of SA nano-crystal EEPROM cells. The logic functionality below the lithography limit derived from the SA dot arrays and the I-V characteristics including the Coulomb blockade effect are then presented. (C) 2000 Academic Press.