Via hole technology for thin-film transistor circuits

被引:15
作者
Gleskova, H [1 ]
Wagner, S [1 ]
Zhang, Q [1 ]
Shen, DS [1 ]
机构
[1] UNIV ALABAMA,DEPT ELECT & COMP ENGN,HUNTSVILLE,AL 35899
关键词
D O I
10.1109/55.641433
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays, The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.
引用
收藏
页码:523 / 525
页数:3
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