Comparison of key performance metrics in two- and three-dimensional integrated circuits

被引：25

作者：

Rahman, A ^{[1
]}

Fan, A ^{[1
]}

Reif, R ^{[1
]}

机构：

[1] MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA

来源：

PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2000年

关键词：

D O I：

10.1109/IITC.2000.854268

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper some key performance metrics in two-dimensional (2-D) and three-dimensional (3-D) integrated circuits (IC) are estimated for scaled technologies from 250-nm to 50-nm technology nodes using a system-level modeling approach [1], [2]. Considering a microprocessor as an example, projections are made for performance metrics such as clock frequency, chip area, interconnect delay and repeater's number for 2-D and 3-D implementation.

引用

页码：18 / 20

页数：3

共 7 条

[1]

Bakoglu H., 1990, CIRCUITS INTERCONNEC

[2]

Bohr MT, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P241, DOI 10.1109/IEDM.1995.499187

[3] A stochastic wire-length distribution for gigascale integration (GSI) - Part I: Derivation and validation [J].