Long lossy lines (L-3) and their impact upon large chip performance

The semiconductor industry expects the performance of microprocessors to continue at its current rate of improvement; i.e., clock rates should double every two to three years, This is a commendable goal but it is also fair to question whether this is an achievable goal, The fundamental problem is that as groundrules are reduced, the natural tendency is to make smaller conductor cross-sectional areas, The result is a high resistance line that exhibits slow wave propagation effects [1], This reduces the general performance expectations, As circuits become faster and denser on the chip, line delays become greater than expected, This problem will be analyzed and potential chip and packaging solutions will be offered, Clock rate predictions for various design and process options will be made. A tactical recommendation to consider a total packaged electronics solution is presented.