Bias stress induced threshold voltage shift in pentacene thin-film transistors

Threshold voltaue instabilities in SiO2/polyimide dual-gate dielectric pentacene thin-film transistors are investigated as a function. of bias stress time for 1060 s at temperatures between 260 and 340 K in nitrogen atmosphere. Field-effect mobility maintains constant values at every measurement temperature during the application of constant bias stress voltage. The threshold voltage shift at all measurement temperatures is described by the stretched exponential stress time dependence of Delta V-th(t) = Delta V-th0{1 - exp[-(t/tau)(beta)]}. These experimental results suggest that our threshold voltage shift can be interpreted as carrier injection from the pentacene channel into traps located at the channel/gate dielectric interface.