The digital front-end electronics for the space-borne INTEGRAL-SPI experiment:: ASIC design, design for test strategies and self-test facilities

被引：2

作者：

Mur, M ^{[1
]}

Cordier, B ^{[1
]}

Donati, M ^{[1
]}

Duc, R ^{[1
]}

Fallou, JL ^{[1
]}

Larqué, T ^{[1
]}

Louis, F ^{[1
]}

Schanne, S ^{[1
]}

Zonca, E ^{[1
]}

机构：

[1] CEA Saclay, DSM, DAPNIA, SEDI, F-91191 Gif Sur Yvette, France

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2002年 / 49卷 / 05期

关键词：

application specific integrated circuit (ASIC) design; built-in-self-test; design-for-test;

D O I：

10.1109/TNS.2002.803855

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The flight model of the digital front-end electronics (DFEE) of the gamma-ray spectrometer SPI has been recently integrated on the INTEGRAL satellite spacecraft. The processing core of the DFEE is based on a dedicated application specific integrated circuit (ASIC). We report on the unified design and test methodology that was deployed to cover the entire life cycle of this subsystem, from initial design simulation to operational self-test and diagnosis operations after launch. Strong emphasis is put on the ASIC design-for-test strategies, from very-high speed integrated circuit description language IEEE 1076 (VHDL) simulation and test bench validation to full scan fabrication test coverage and in-flight self-test capability.

引用

页码：2492 / 2496

页数：5