A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs

被引：151

作者：

Chen, Q ^{[1
]}

Agrawal, B

Meindl, JD

机构：

[1] Georgia Inst Technol, Microelect Res Ctr, Atlanta, GA 30332 USA

[2] IBM Corp, EDA Lab, Hopewell Jct, NY 12533 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 06期

关键词：

double-gate MOSFET; MOSFETs; scale length; scaling; subthreshold swing; undoped;

D O I：

10.1109/TED.2002.1003757

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A general analytical subthreshold swing (S) model for symmetric DG MOSFETs is derived using evanescent-mode analysis. Through a concept of effective conducting path, it explains a unique doping concentration (N(A)) dependence of S, providing a unified understanding of previous S models and leading to a new improved S model for undoped DG MOSFETs. Compact, explicit expressions of a scale length are derived, which expedite projections of scalability of DG MOSFETs and its requirement.

引用

页码：1086 / 1090

页数：5

共 13 条

[1]

AGRAWAL B, 1994, THESIS RENSSELAER PO

[2]

FOSSUM JG, 2001, P DIG GOV MICR APPL, P322

[3]

Frank D. J., 1992, International Electron Devices Meeting 1992. Technical Digest (Cat. No.92CH3211-0), P553, DOI 10.1109/IEDM.1992.307422

[4] Generalized scale length for two-dimensional effects in MOSFET's [J].

Frank, DJ ;

Taur, Y ;

Wong, HSP .

IEEE ELECTRON DEVICE LETTERS, 1998, 19 (10) :385-387

[5]

Monroe D., 1998, P IEEE INT SOI C, P157

[6] Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs [J].

Oh, SH ;

Monroe, D ;

Hergenrother, JM .

IEEE ELECTRON DEVICE LETTERS, 2000, 21 (09) :445-447

[7]

Ren ZB, 2000, INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, P715, DOI 10.1109/IEDM.2000.904418

[8] Electronic structures and phonon-limited electron mobility of double-gate silicon-on-insulator Si inversion layers [J].

Shoji, M ;

Horiguchi, S .

JOURNAL OF APPLIED PHYSICS, 1999, 85 (05) :2722-2731

[9] SCALING THEORY FOR DOUBLE-GATE SOI MOSFETS [J].

SUZUKI, K ;

TANAKA, T ;

TOSAKA, Y ;

HORIE, H ;

ARIMOTO, Y .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (12) :2326-2329

[10] Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs [J].

Taur, Y .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (12) :2861-2869

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