A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

被引：34

作者：

Lu, JQ ^{[1
]}

Kwon, Y ^{[1
]}

Rajagopalan, G ^{[1
]}

Gupta, M ^{[1
]}

McMahon, J ^{[1
]}

Lee, KW ^{[1
]}

Kraft, RP ^{[1
]}

McDonald, JF ^{[1
]}

Cale, TS ^{[1
]}

Gutmann, RJ ^{[1
]}

Xu, B ^{[1
]}

Eisenbraun, E ^{[1
]}

Castracane, J ^{[1
]}

Kaloyeros, A ^{[1
]}

机构：

[1] Rensselaer Polytech Inst, Focus Ctr, Troy, NY 12180 USA

来源：

PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2002年

关键词：

D O I：

10.1109/IITC.2002.1014893

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A viable approach for a monolithic wafer-scale three-dimensional (3D) IC technology platform is presented, focusing on wafer bonding, wafer thinning and inter-wafer damascene-patterned interconnects. Principal results include successful wafer alignment, wafer bonding with both BCB and Flare, post bonding wafer thinning using grinding and polishing to 35-50 mum, and via etch through the required material stack.

引用

页码：78 / 80

页数：3