New channel percolation model for VT shift in discrete-trap memories

被引：15

作者：

Ielmini, D ^{[1
]}

Compagnoni, CM ^{[1
]}

Spinelli, AS ^{[1
]}

Lacaita, AL ^{[1
]}

Gerardi, C ^{[1
]}

机构：

[1] Politecn Milan, Dipartimento Elettr & Informat, I-20133 Milan, Italy

来源：

2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/RELPHY.2004.1315382

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work we studied the mechanisms for channel conduction in discrete-trap memories (DTMs). It is shown that the threshold voltage V-T in the cell corresponds to a percolation condition in the channel, where the inverted layers connect source to drain. A numerical model is presented which is able to calculate the local profile of V-T in the channel, and to evaluate the global V-T in the cell according to a channel percolation condition. The model is shown to account for the size dependence of V-T in DTM cells, and for the staircase charge-loss characteristics observed on ultrascaled devices. The implications of the percolation mechanism from the reliability point of view are finally discussed in details.

引用

页码：515 / 521

页数：7

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