High energy-barrier for defect creation in thin-film transistors based on hot-wire amorphous silicon

Thin-film transistors based on amorphous silicon deposited by hot-wire chemical-vapor deposition (CVD) exhibited a high mean barrier height of 1.074 eV for defect creation after gate-voltage stress. This is 77 meV higher than for glow-discharge devices. Transistors with a SiO2 or a-SiNx:H gate dielectric showed good performance with a field-effect mobility up to 0.7 cm(2)/V s. Thus, good thin-film transistors with a superior stability can be deposited by hot-wire CVD at high deposition rates of 1.7 nm/s. We demonstrate that a reduced defect creation in the silicon and not the hot-wire-specific absence of interface ion bombardment is responsible for this higher stability. (C) 1999 American Institute of Physics. [S0003-6951(99)03749-3].