A Comprehensive Power-Performance Model for NoCs with Multi-Flit Channel Buffers

Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a crucial element affecting the overall system performance, On the other hand, technology improvements may lead to much energy consumption in micro-routers of an on-chip network. This necessitates an exhaustive analysis of NoCs for future designs. This paper presents a comprehensive analytical model to predict message latency for different data flows traversing across the network. This model considers channel buffers of multiple flits which were not previously studied in NoC context. Also, architectural descriptions of the overall consumed power in the network components are extracted considering message arrival and service rates. The results obtained from simulation experiments confirm that the proposed performance and power models exhibit good accuracy for various network configurations and workloads.