共 6 条
[2]
Alvandpour A, 2003, ISSCC DIG TECH PAP I, V46, P112
[3]
[Anonymous], IEEE ISSCC
[4]
A 4GHz 130nm address generation unit with 32-bit sparse-tree adder core
[J].
2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS,
2002,
:126-127
[5]
SAGER D, 2001, ISSCC, P324
[6]
THOMPSON S, 2000, IEDM TECHNICAL DIGES, P61