Modeling of interconnect capacitance, delay, and crosstalk in VLSI

被引：157

作者：

Wong, SC ^{[1
]}

Lee, GY

Ma, DJ

机构：

[1] Winbond Elect Corp, Technol Dev Ctr, Hsinchu, Taiwan

[2] Natl Chiao Tung Univ, Inst Elect Engn, Hsinchu, Taiwan

[3] Natl Chung Hsing Univ, Dept Elect Engn, Taichung 40227, Taiwan

来源：

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | 2000年 / 13卷 / 01期

关键词：

closed-form models; delay and crosstalk; interconnect capacitance; simulations;

D O I：

10.1109/66.827350

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in very large scale integration (VLSI), namely, 1) parallel lines on a plane and 2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson's equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations.

引用

页码：108 / 111

页数：4

共 8 条

[1] Modeling and extraction of interconnect capacitances for multilayer VLSI circuits [J].