CLOSED-FORM EXPRESSIONS FOR INTERCONNECTION DELAY, COUPLING, AND CROSSTALK IN VLSIS

被引:395
作者
SAKURAI, T
机构
[1] The Semiconductor Device Engineering Laboratory, Toshiba Corporation, Kawasaki
关键词
D O I
10.1109/16.249433
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Controlling RC interconnection delay is the key to high-speed VLSI designs [1], [2]. In this paper, a closed-form formula for a waveform of the RC line with practical boundary conditions is derived for the first time. Expressions are also derived for a voltage slope and transition time of the RC interconnection. Other important issues related to interconnections are capacitive coupling of two lines and crosstalk induced by the capacitive coupling. Expressions are derived for a coupling capacitance and a crosstalk voltage height, which can be used in VLSI designs. Using the expressions, optimum linewidth that minimizes RC delay, and the trend of RC delay in the scaled-down VLSI's are discussed.
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页码:118 / 124
页数:7
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