A UNIFIED THEORY FOR MIXED CMOS BICMOS BUFFER OPTIMIZATION

A simple yet realistic gate sizing theory is presented to optimize delay of a cascaded gate buffer. The theory is based on the fact that CMOS/BiCMOS gate delay is linearly dependent on fan-out f, that is, the delay can be expressed as Af + B, where A and B are coefficients. The optimum fan-out f(OPT) is shown to be approximated as e + B/1.5A for a gate chain. The theory covers various BiCMOS/CMOS gate types such as NAND's and NOR'S in a unified framework. The existence of spurious capacitance is shown to increase the size of all transistors compared with the case without the spurious capacitance.