Paradigm shift for NBTI characterization in ultra-scaled CMOS technologies

Despite large efforts given by the semiconductor community to overcome NBTI challenges in ultra-thin gate dielectrics, both the understanding of mechanisms [1-9] and the characterization methodology are not completely achieved yet. It is well accepted that the mechanisms lying behind NBTI are the interface traps generation, the fixed charges build-up and the hole trapping in the gate oxide [8]. The effort is devoted reducing the inherent recovery during the NBTI characterization. 'Me standard methodology [12] has been shown to have serious effects on the degradation itself [13, 11, 8]. In this context and since the degradation is not permanent but recoverable, we propose in this work a new framework to manage NBTI in ultra-scaled technologies. This takes into account both the recoverable proportion of the degradation, which is studied in the first part of the paper, and the electrical parameter legitimacy for DC and AC modes analysis developed in the second part.