The Clear-PEM electronics system

被引:15
作者
Albuquerque, Edgar [1 ]
Bento, Pedro
Leong, Carlos
Goncalves, Fernando
Nobre, Joao
Rego, Joel
Relvas, Paulo
Lousa, Pedro
Rodrigues, Pedro
Teixeira, Isabel C.
Teixeira, Joao P.
Silva, Luis
Silva, M. Medeiros
Trindade, Andreia
Varela, Joao
机构
[1] INESC, ID, Lisbon, Portugal
[2] Univ Tecn Lisboa, IST, P-1100 Lisbon, Portugal
[3] INOV, Lisbon, Portugal
[4] LIP, P-1000 Lisbon, Portugal
[5] CERN, Geneva, Switzerland
关键词
D O I
10.1109/TNS.2006.881650
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The Clear-PEM detector system is a compact positron emission mammography scanner with about 12000 channels aiming at high sensitivity and good spatial resolution. Front-end, Trigger, and Data Acquisition electronics are crucial components of this system. The on-detector front-end is implemented as a data-driven synchronous system that identifies and selects the analog signals whose energy is above a predefined threshold. The off-detector trigger logic uses digitized front-end data streams to compute pulse amplitudes and timing. Based on this information it generates a coincidence trigger signal that is used to initiate the conditioning and transfer of the relevant data to the data acquisition computer. To minimize dead-time, the data acquisition electronics makes extensive use of pipeline processing structures and derandomizer memories with multievent capacity. The system operates at 100-MHz clock frequency, and is capable of sustaining a data acquisition rate of I million events per second with an efficiency above 95 %, at a total single photon background rate of 10 MHz. The basic component of the front-end system is a low-noise amplifier-multiplexer chip presently under development. The off-detector system is designed around a dual-bus crate backplane for fast intercommunication between the system boards. The trigger and data acquisition logic is implemented in large FPGAs with 4 million gates. Monte Carlo simulation results evaluating the trigger performance, as well as results of hardware simulations are presented, showing the correctness of the design and the implementation approach.
引用
收藏
页码:2704 / 2711
页数:8
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