A merged single-electron transistor and metal-oxide-semiconductor transistor logic for interface and multiple-valued functions

被引：18

作者：

Inokawa, H ^{[1
]}

Fujiwara, A ^{[1
]}

Takahashi, Y ^{[1
]}

机构：

[1] NTT Corp, Basic Res Labs, Atsugi, Kanagawa 2430198, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS | 2002年 / 41卷 / 4B期

关键词：

SET; MOSFET; CMOS; interface circuit; multiple-valued function; voltage gain; output amplitude;

D O I：

10.1143/JJAP.41.2566

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

A merged single-electron transistor and metal-oxide-semiconductor transistor logic is introduced that features large voltage gain and output amplitude that far exceed the limits of Cg/Cd and e/C-Sigma inherent to a single-electron transistor (SET), where C-g, C-d, e, and C-Sigma are gate capacitance, drain capacitance. elemental charge, and the total capacitance around the Coulomb island, respectively. The operation of the proposed logic is verified with devices fabricated by the complementary metal-oxide-semiconductor (CMOS)-compatible pattern-dependent oxidation process. The proposed logic is not only suitable for a SET-to-CMOS inter-face circuit, but is also useful as a basic element for multiple-valued functions.

引用

页码：2566 / 2568

页数：3