Hierarchical approach to "atomistic" 3-D MOSFET simulation

被引:67
作者
Asenov, A [1 ]
Brown, AR
Davies, JH
Saini, S
机构
[1] Univ Glasgow, Dept Elect & Elect Engn, Glasgow G12 8LT, Lanark, Scotland
[2] NASA, Ames Res Ctr, Moffett Field, CA 94035 USA
基金
美国国家航空航天局;
关键词
deep submicron; device models; modeling; simulation; very large scale integration (VLSI);
D O I
10.1109/43.806802
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present a hierarchical approach to the "atomistic" simulation of aggressively scaled sub-0.1-mu m MOSFET's, These devices are so small that their characteristics depend on the precise location of dopant atoms within them, not just on their average density. A full-scale three-dimensional drift-diffusion atomistic simulation approach is first described and used to verify more economical, but restricted, options, To reduce processor time and memory requirements at high drain voltage, we have developed a self-consistent option based on a solution of the current continuity equation restricted to a thin slab of the channel. This is coupled to the solution of the Poisson equation in the whole simulation domain in the Gummel iteration cycles. The accuracy of this approach is investigated in comparison to the full self-consistent solution. At low drain voltage, a single solution of the nonlinear Poisson equation is sufficient to extract the current with satisfactory accuracy. In this case, the current is calculated by solving the current continuity equation in a drift approximation only, also in a thin slab containing the MOSFET channel. The regions of applicability for the different components of this hierarchical approach are illustrated in example simulations covering the random dopant-induced threshold voltage fluctuations, threshold voltage lowering, threshold voltage asymmetry, and drain current fluctuations.
引用
收藏
页码:1558 / 1565
页数:8
相关论文
共 24 条
[1]   Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's:: A 3-D "atomistic" simulation study [J].
Asenov, A .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (12) :2505-2513
[2]  
ASENOV A, 1998, 98EX116 IEEE, P58
[3]  
ASENOV A, 1996, J SIMULATION PRACTIC, V4, P155
[4]  
ASENOV A, IN PRESS NANOTECHNOL
[5]  
BURNETT D, TECH DIG S 94, P15
[6]  
DE VK, TECH DIG VLSI S 96, P198
[7]  
DITBUISSON OR, P ESSDERC 96, P731
[8]  
Eisele M, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P67, DOI 10.1109/IEDM.1995.497184
[9]  
Gilma G. H., 1998, Simulation of Semiconductor Processes and Devices 1998. SISPAD 98, P46