Speed and power scaling of SRAM's

被引：68

作者：

Amrutur, BS ^{[1
]}

Horowitz, MA ^{[1
]}

机构：

[1] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 02期

关键词：

delay scaling; power scaling; scaling; speed scaling; static random access memory (SRAM); technology scaling;

D O I：

10.1109/4.823443

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Simple models for the delay, power, and area of a static random access memory (SRAM) are used to determine the optimal organizations for a SRAM and study the scaling of their speed and power with size and technology. The delay is found to increase by about one gate delay for every doubling of the RAM-size up to 1 Mb, beyond which the interconnect delay becomes an increasingly significant fraction of the total delay. With technology sealing, the nonscaling of threshold mismatches in the sense amplifiers is found to significantly impact the total delay in generations of 0.1 mu m and below.

引用

页码：175 / 185

页数：11