Single crystal nanowire vertical surround-gate field-effect transistor

被引:592
作者
Ng, HT [1 ]
Han, J [1 ]
Yamada, T [1 ]
Nguyen, P [1 ]
Chen, YP [1 ]
Meyyappan, M [1 ]
机构
[1] NASA, Ames Res Ctr, Ctr Nanotechnol, Moffett Field, CA 94035 USA
关键词
D O I
10.1021/nl049461z
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
Harnessing the potential of single crystal inorganic nanowires for practical advanced nanoscale applications requires not only reproducible synthesis of highly regular one-dimensional (1D) nanowire arrays directly on device platforms but also elegant device integration which retains structural integrity of the nanowires while significantly reducing or eliminating complex critical processing steps. Here we demonstrate a unique, direct, and bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field-effect transistor (VSG-FET). The vertical device structure and bottom-up integration reduce process complexity, compared to conventional top-down approaches. More significantly, scaling of the vertical channel length is lithographically independent and decoupled from the device packing density. A bottom electrical contact to the nanowire is uniquely provided by a heavily doped underlying lattice-match substrate. Based on the nanowire-integrated platform, both n- and p-channel VSG-FETs are fabricated. The vertical device architecture has the potential for use in tera-level ultrahigh-density nanoscale memory and logic devices.
引用
收藏
页码:1247 / 1252
页数:6
相关论文
共 26 条
  • [1] AUTH CP, 1998, THESIS STANFORD U
  • [2] Transparent ZnO thin-film transistor fabricated by rf magnetron sputtering
    Carcia, PF
    McLean, RS
    Reilly, MH
    Nunes, G
    [J]. APPLIED PHYSICS LETTERS, 2003, 82 (07) : 1117 - 1119
  • [3] Electronically configurable molecular-based logic gates
    Collier, CP
    Wong, EW
    Belohradsky, M
    Raymo, FM
    Stoddart, JF
    Kuekes, PJ
    Williams, RS
    Heath, JR
    [J]. SCIENCE, 1999, 285 (5426) : 391 - 394
  • [4] Novel ultrahigh-density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell
    Endoh, T
    Kinoshita, K
    Tanigami, T
    Wada, Y
    Sato, K
    Yamada, K
    Yokoyama, T
    Takeuchi, N
    Tanaka, K
    Awaya, N
    Sakiyama, K
    Masuoka, F
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (04) : 945 - 951
  • [5] Huang MH, 2001, ADV MATER, V13, P113, DOI 10.1002/1521-4095(200101)13:2<113::AID-ADMA113>3.0.CO
  • [6] 2-H
  • [7] Electronic properties of multiwalled carbon nanotubes in an embedded vertical array
    Li, J
    Stevens, R
    Delzeit, L
    Ng, HT
    Cassell, A
    Han, J
    Meyyappan, M
    [J]. APPLIED PHYSICS LETTERS, 2002, 81 (05) : 910 - 912
  • [8] Single- and multi-wall carbon nanotube field-effect transistors
    Martel, R
    Schmidt, T
    Shea, HR
    Hertel, T
    Avouris, P
    [J]. APPLIED PHYSICS LETTERS, 1998, 73 (17) : 2447 - 2449
  • [9] MASUOKA F, 2004, 1 INT S SYST CONSTR
  • [10] NEUDECK PG, 2000, VLSI HDB ELECT ENG H