Hiding synchronization delays in a GALS processor microarchitecture

被引：9

作者：

Semeraro, G ^{[1
]}

Albonesi, DH ^{[1
]}

Magklis, G ^{[1
]}

Scott, ML ^{[1
]}

Dropsho, SG ^{[1
]}

Dwarkadas, S ^{[1
]}

机构：

[1] Rochester Inst Technol, Dept Comp Engn, Rochester, NY 14623 USA

来源：

10TH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/ASYNC.2004.1299297

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We analyze an Alpha 21264-like Globally-Asynchronous, Locally-Synchronous (GALS) processor organized as a Multiple Clock Domain (MCD) microarchitecture and identify the architectural features of the processor that influence the limited performance degradation measured We show that the out-of-order superscalar execution features of a processor, which allow traditional instruction execution latency to be hidden, are the same features that reduce the Performance degradation impact of the synchronization costs of an MCD processor In the case of our Alpha 21264-like processor, up to 94% of the MCD synchronization delays are hidden and do not impact overall performance. In addition, we show that by adding out-of-order superscalar execution capabilities to a simpler microarchitecture, such as an Intel StrongARM-like processor, as much as 62% of the performance degradation caused by synchronization delays can be eliminated.

引用

页码：159 / 169

页数：11

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