Power-aware scheduling for AND/OR graphs in real-time systems

被引:59
作者
Zhu, D [1 ]
Mossé, D [1 ]
Melhem, R [1 ]
机构
[1] Univ Pittsburgh, Dept Comp Sci, Pittsburgh, PA 15260 USA
关键词
power-aware scheduling; AND/OR; real-time systems;
D O I
10.1109/TPDS.2004.45
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Power aware computing has become popular recently and many techniques have been proposed to manage processor energy consumption for traditional real-time applications. In this paper, we are concerned mainly with the AND/OR model of real-time applications that have different execution paths consisting of different tasks. The contribution of this paper is twofold. First, we propose a greedy slack stealing algorithm to deal with applications represented by AND/OR graphs and prove its correctness in terms of meeting the timing constraints. Then, using statistical information about the applications, we propose a few variations of speculative scheduling algorithms that intend to save energy by reducing the number of speed changes ( and, thus, the overhead) while ensuring that the application meets its timing constraints. Some practical issues are also considered, such as shared memory access contention and idle energy consumption. The performance of the algorithms is analyzed with respect to processor energy savings. The results surprisingly show that the greedy slack stealing scheme is better than some speculative schemes and that the greedy scheme is good enough when a reasonable minimal speed exists in the system or when there are only a few (four to six) voltage/speed levels.
引用
收藏
页码:849 / 864
页数:16
相关论文
共 26 条
[1]  
ABOUGHAZALEH N, 2001, P WORKSH COMP OP SYS
[2]  
[Anonymous], P INT PAR DISTR PROC
[3]  
AYDIN H, 2001, P 22 IEEE REAL TIM S
[4]  
Burd T. D., 1995, Proceedings of the Twenty-Eighth Hawaii International Conference on System Sciences, P288, DOI 10.1109/HICSS.1995.375385
[5]   A dynamic voltage scaled microprocessor system [J].
Burd, TD ;
Pering, TA ;
Stratakos, AJ ;
Brodersen, RW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (11) :1571-1580
[6]  
BURGER D, 1997, 1342 U WISC MAD DEP
[7]  
Chandrakasan A., 1996, P INT S LOW POW EL D
[8]   LOW-POWER CMOS DIGITAL DESIGN [J].
CHANDRAKASAN, AP ;
SHENG, S ;
BRODERSEN, RW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) :473-484
[9]   MULTIPROCESSOR ONLINE SCHEDULING OF HARD-REAL-TIME TASKS [J].
DERTOUZOS, ML ;
MOK, AKL .
IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, 1989, 15 (12) :1497-1506
[10]  
Ernst R, 1997, 1997 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, P598, DOI 10.1109/ICCAD.1997.643600