Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: Practical design aspects

被引：278

作者：

Anelli, G ^{[1
]}

Campbell, M

Delmastro, M

Faccio, F

Florian, S

Giraldo, A

Heijne, E

Jarron, P

Kloukinas, K

Marchioro, A

Moreira, P

Snoeys, W

机构：

[1] CERN, CH-1211 Geneva 23, Switzerland

[2] Univ Padua, I-35131 Padua, Italy

[3] Ist Nazl Fis Nucl, I-35131 Padua, Italy

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1999年 / 46卷 / 06期

关键词：

D O I：

10.1109/23.819140

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO2), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn.

引用

页码：1690 / 1696

页数：7

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