Porous organosilicates for on-chip dielectric applications

被引：25

作者：

Miller, RD ^{[1
]}

Beyers, R ^{[1
]}

Carter, KR ^{[1
]}

Cook, RF ^{[1
]}

Harbison, M ^{[1
]}

Hawker, CJ ^{[1
]}

Hedrick, JL ^{[1
]}

Lee, V ^{[1
]}

Liniger, E ^{[1
]}

Nguyen, C ^{[1
]}

Remenar, J ^{[1
]}

Sherwood, M ^{[1
]}

Trollsås, M ^{[1
]}

Volksen, W ^{[1
]}

Yoon, DY ^{[1
]}

机构：

[1] IBM Corp, Almaden Res Ctr, San Jose, CA 95120 USA

来源：

LOW-DIELECTRIC CONSTANT MATERIALS V | 1999年 / 565卷

关键词：

D O I：

10.1557/PROC-565-3

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Porous organosilicates useful for on-chip insulator applications can be prepared by templating the vitrification of low molecular weight silsesquioxanes (SSQs) using highly branched, thermally labile macromolecules which are subsequently removed in a thermal process to generate porosity. The process involves spin coating a mixture of the matrix material and the porogen (pore generator) followed by thermal curing to initiate vitrification and decomposition of the porogen. The morphology is fixed during the formation of the nanoscopic inorganic-organic hybrid and is maintained during foaming. This process generates controllable and stable morphologies where the void volume is determined by the porogen loading level. The porous materials are thermally robust and intrinsically hydrophobic without subsequent chemical treatment. Dielectric constants of < 2.2 are easily achieved for pore volumes of only 20%, and this porosity appears to be predominately closed cell in nature. These materials display a number of thermal mechanical and electric properties consistent with the requirements for on-chip insulator applications.

引用

页码：3 / 15

页数：13

共 38 条

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