Effects of hot-carrier degradation in analog CMOS circuits

In this paper a method is presented that allows to quantify the effects of hot carrier degradation on analog CMOS circuits. Specific features of hot carrier degradation related to analog CMOS operation are discussed in detail. On this basis single transistor stress experiments are defined monitoring analog operation and conclusions are drawn for the choice of analog hot carrier lifetime criteria. A general method is presented which establishes a relation between single transistor stress results and circuit parameter degradation. Examples for the applicability of this method are given, presenting measured data of hot-carrier-induced parameter shifts of analog sub-circuits.