Fabrication and performance of selective HSG storage cells for 256 Mb and 1 Gb DRAM applications

被引:14
作者
Banerjee, A [1 ]
Wise, RL
Plumton, DL
Bevan, M
Pas, MF
Crenshaw, DL
Aoyama, S
Mansoori, MM
机构
[1] Texas Instruments Inc, Dallas, TX 75243 USA
[2] Tokyo Elect Ltd, Yamanashi 4070192, Japan
[3] Adv Semicond Mat Amer, Phoenix, AZ 85034 USA
关键词
capacitor; DRAM chips; semiconductor films;
D O I
10.1109/16.824734
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Fabrication of rapid thermal nitrided HSG transformed crown capacitor storage cells incorporating an ultrathin low pressure chemical vapor deposition (LPCVD) Ta2O5 and Si3N4/SiO2(NO) dielectric is proposed, 256 Mb array with HSG crown cells of 0.3 mu m diameter x 0.6 mu m height and 49 A T-eff showed an area enhancement factor of 1.7 (relative to untransformed crown cell), C-min/C-max ratio of >0.95, and capacitance of 16.7 fF/cell is obtained. A measured leakage current density of 0.7 nA/cm(2) at 1.2 V is reported. Metal-oxide-semiconductor capacitor (MOSCAP) devices with HSG electrode for 1 Gb application are characterized using capacitance-voltage (C-V) and current-voltage (I-V) analyses. Detailed HSG grain characterization results are presented with correlation to the electrical behavior of the devices. Devices are formed using LPCVD Ta2O5 and/or Si3N4 dielectric. HSG films formed from 4 x 10(20) atoms/cc phosphorus doped amorphous silicon show depletion in C-V behavior. It is shown that phosphine doping of HSG film is required to avoid depletion. Process selectivity of UHV/CVD HSG transformation mechanism applied to thermal oxide and nitride field dielectrics is fully explored. Selectivity limits for different types of dielectric are also presented. Effect of critical parameters such as a-Si dopant concentration, HSG incubation time, anneal conditions, and a-Si layer thickness on HSG transformation are discussed for 1 Gb crown cells.
引用
收藏
页码:584 / 592
页数:9
相关论文
共 5 条
  • [1] Rugged surface polycrystalline silicon film deposition and its application in a stacked dynamic random access memory capacitor electrode
    Ino, M
    Miyano, J
    Kurogi, H
    Tamura, H
    Nagatomo, Y
    Yoshimaru, M
    [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1996, 14 (02): : 751 - 756
  • [2] Process and device technologies for 1 Gbit dynamic random-access memory cells
    Kaga, T
    Ohkura, M
    Murai, F
    Yokoyama, N
    Takeda, E
    [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1995, 13 (06): : 2329 - 2334
  • [3] Kamiyama S., 1993, International Electron Devices Meeting 1993. Technical Digest (Cat. No.93CH3361-3), P49, DOI 10.1109/IEDM.1993.347401
  • [4] HEMISPHERICAL GRAINED SI FORMATION ON IN-SITU PHOSPHORUS-DOPED AMORPHOUS-SI ELECTRODE FOR 256MB DRAMS CAPACITOR
    WATANABE, H
    TATSUMI, T
    OHNISHI, S
    KITAJIMA, H
    HONMA, I
    IKARASHI, T
    ONO, H
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (07) : 1247 - 1254
  • [5] WATANABE H, 1992, SOLID STATE TECH JUL, P29