A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP

An MIMD multiprocessor digital signal- processing (DSP), chip containing four 64-b processing elements (PE's) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a,32-6 RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PE's are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory; multiprocessing using a modified-MESI data coherency protocol, High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PE's. Process synchronization is achieved using cached semaphores. The 200-mm(2), 0.25-mu m CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply.