共 11 条
- [11] WESTE N, 1992, PRINCIPLES CMOS VLSI, pCH8
A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP
被引：41
作者：
Ackland, B
Anesko, A
Brinthaupt, D
Daubert, SJ
Kalavade, A
Knobloch, J
Micca, E
Moturi, M
Nicol, CJ
O'Neill, JH
Othmer, J
Säckinger, E
Singh, KJ
Sweet, J
Terman, CJ
Williams, J
机构：
[1] Bell Labs, Lucent Technol, DSP & VLSI Syst Res, Holmdel, NJ 07733 USA
[2] Lucent Technol, Microelect Grp, Holmdel, NJ 07733 USA
[3] MIT, Comp Sci Lab, Cambridge, MA 02139 USA
关键词：
digital signal processor;
multiprocessing systems;
multiprocessor interconnection;
split-transaction bus;
D O I：
10.1109/4.826824
中图分类号：
TM [电工技术];
TN [电子技术、通信技术];
学科分类号：
0808 ;
0809 ;
摘要：
An MIMD multiprocessor digital signal- processing (DSP), chip containing four 64-b processing elements (PE's) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a,32-6 RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PE's are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory; multiprocessing using a modified-MESI data coherency protocol, High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PE's. Process synchronization is achieved using cached semaphores. The 200-mm(2), 0.25-mu m CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply.
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页码：412 / 424
页数：13
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