Analysis of the hot-carrier degradation of deep-submicrometer large-angle-tilt-implanted drain (LATID) MOSFETs

The hot carrier degradation of large-angle-tilt implanted drain (LATID) and standard LDD N-MOSFETs has been investigated thoroughly using the combination of I-V characterization, charge-pumping and profiling of the damaged region. Although the LATID structure exhibits a good current drivability and net improvement in the hut-carrier immunity, the gate-voltage dependence of the transistor degradation shows significant differences compared to the LDD structure. The distinct time-dependence of the transconductance degradation and the filling of acceptor-like (neutral) oxide traps were emphasized. It is shown that the degradation in LATID is less sensitive to the gate-voltage V-g governing hole or electron injection, which leads to a ''flat'' V-g-dependence where holes are less efficient to create acceptor-like oxide traps. The charge-pumping analysis has shown a similar V-g-dependence between the interface trap generation and the acceptor-like oxide traps in both structures. Less positive and negative trapped charges are found in LATID than in LDD with a larger difference in the high V-g-stress region (where the trapping of negative charge largely dominates the interface trap generation). This was confirmed by profiling measurements which have shown that the density of the negative trapped charges in LATID is one half of that in LDD, but in contrast presents a significant extension from the n-region into the channel. Finally, though the LATID N-MOSFET is one of the best structures able to exceed a DC lifetime of 10 years, lifetime experiments have shown that accepter-like oxide traps clearly reduce the device lifetime in LATID in the same way as in LDD, which could lead to enhanced hot-carrier degradation in some cases of AC operation for these structures. (C) 1997 Elsevier Science Ltd.