Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOICMOS

Source/drain (S/D) engineering for an ideal box-shaped junction formation using laser annealing (LA) combined with pre-amorphization implantation (PAI) is proposed and implemented to the device integration for sub-100-nm CMOS on SOI substrate. Modeling analysis for resistance component associated with abruptness of junction profile demonstrates noticeable reduction in parasitic series resistance with technology generation can be achieved through the junction profile slope engineering. From the experimental results of LA process, it is found out that PAI not only controls the ultrashallow junction depth precisely, but also reduces laser energy fluence required for impurity activation. In addition, laser annealing energy can be further reduced by use of SOI substrate in the device integration, indicating the implementation feasibility of LA process to CMOS integration with enlarged process window margin. The proposed S/D engineering is verified by the sheet resistance of junctions and the fabricated device current characteristics exhibiting the substantially improved short-channel performance with higher current capability due to box-shaped junction profile as compared with conventional rapid thermal-annealed (RTA) devices.