Material and process limits in silicon VLSI technology

被引:119
作者
Plummer, JD [1 ]
Griffin, PB [1 ]
机构
[1] Stanford Univ, Stanford, CA 94305 USA
关键词
dielectric materials; MOSFETs; semiconductor device doping; semiconductor device fabrication; silicon;
D O I
10.1109/5.915373
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The integrated circuit (IC) industry has followed a steady path of shrinking device geometries for more than 30 years. It is widely believed that this process will continue for at least another ten years. However there are increasingly difficult materials and technology problems to be solved over the next decade if this is to actually occur and, beyond ten years. there is great uncertainly. about the ability to continue scaling metal-oxide-semiconductor field-effect transistor (MOSFET) structures. This paper describes some of the most challenging materials and process issues to be faced in the future and, where possible solutions are known, describes these potential solutions. The paper is written with the underlying assumption that the basic metal-oxide-semiconductor (MOS) transistor will remain the dominant switching: device used in ICs and it further assumes that silicon will remain the dominant substrate material.
引用
收藏
页码:240 / 258
页数:19
相关论文
共 56 条
[1]   Boron-enhanced-diffusion of boron: The limiting factor for ultra-shallow junctions [J].
Agarwal, A ;
Eaglesham, DJ ;
Gossmann, HJ ;
Pelaz, L ;
Herner, SB ;
Jacobson, DC ;
Haynes, TE ;
Erokhin, Y ;
Simonton, R .
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :467-470
[2]   Reduction of transient diffusion from 1-5 keV Si+ ion implantation due to surface annihilation of interstitials [J].
Agarwal, A ;
Gossmann, HJ ;
Eaglesham, DJ ;
Pelaz, L ;
Jacobson, DC ;
Haynes, TE ;
Erokhin, YE .
APPLIED PHYSICS LETTERS, 1997, 71 (21) :3141-3143
[3]   Intermixing at the tantalum oxide/silicon interface in gate dielectric structures [J].
Alers, GB ;
Werder, DJ ;
Chabal, Y ;
Lu, HC ;
Gusev, EP ;
Garfunkel, E ;
Gustafsson, T ;
Urdahl, RS .
APPLIED PHYSICS LETTERS, 1998, 73 (11) :1517-1519
[4]   Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's [J].
Auth, CP ;
Plummer, JD .
IEEE ELECTRON DEVICE LETTERS, 1997, 18 (02) :74-76
[5]  
Blanks D. K., 1997, P IEEE 24 INT S COMP, P639
[6]  
Byoung Hun Lee, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P133, DOI 10.1109/IEDM.1999.823863
[7]   MOSFET transistors fabricated with high permitivity TiO2 dielectrics [J].
Campbell, SA ;
Gilmer, DC ;
Wang, XC ;
Hsieh, MT ;
Kim, HS ;
Gladfelter, WL ;
Yan, JH .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (01) :104-109
[8]   DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS [J].
DENNARD, RH ;
GAENSSLEN, FH ;
YU, HN ;
RIDEOUT, VL ;
BASSOUS, E ;
LEBLANC, AR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) :256-268
[9]   POINT-DEFECTS AND DOPANT DIFFUSION IN SILICON [J].
FAHEY, PM ;
GRIFFIN, PB ;
PLUMMER, JD .
REVIEWS OF MODERN PHYSICS, 1989, 61 (02) :289-384
[10]   Extremely scaled double-gate CMOS performance projections, including GIDL-controlled off-state current [J].
Fossum, JG ;
Kim, K ;
Chong, Y .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (11) :2195-2200