Integration of capacitor for sub-100-nm DRAM trench technology

被引：13

作者：

Lützen, J ^{[1
]}

Birner, A ^{[1
]}

Goldbach, M ^{[1
]}

Gutsche, M ^{[1
]}

Hecht, T ^{[1
]}

Jakschik, S ^{[1
]}

Orth, A ^{[1
]}

Sänger, A ^{[1
]}

Schröder, U ^{[1
]}

Seidl, H ^{[1
]}

Sell, B ^{[1
]}

Schumann, D ^{[1
]}

机构：

[1] Infineon Technol, IFDD INN, D-01076 Dresden, Germany

来源：

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIT.2002.1015442

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

One of the key enablers in scaling DRAM trench capacitors to sub-100nm ground rules is a viable collar integration concept. We report, for the first time, the successful implementation of a buried collar concept, which leaves ample space for the connection from the array device to the inner electrode. The new collar integration scheme is fully compatible with a number of capacitance enhancement techniques including surface enlargement by trench widening, HSG deposition as well as the utilization of high-k node dielectrics such as Al2O3. These capacitance enhancement techniques are required to maintain a capacitance in excess of 30 fF/cell. In addition, a metal fill of the deep trench will be necessary to maintain a low series resistance of the inner electrode, which is also demonstrated for the first time. The successful integration of these key enablers in deep trenches is presented.

引用

页码：178 / 179

页数：2